Korean Chipmakers Advance 16-Layer HBM4 as Nvidia Rubin Favors 12-Layer Memory

SK hynix and Samsung Electronics are pressing ahead with 16-layer high-bandwidth memory technology even as Nvidia’s next-generation Vera Rubin artificial intelligence platform is expected to use mainly 12-layer HBM4 chips. The outlook eases concern that Rubin might require only eight-layer products, but it also suggests that broad commercial demand for the denser 16-layer format has yet to arrive.

Counterpoint Research said most Rubin-based products are likely to use 12-layer HBM4, reversing an assessment it issued in August that pointed to an eight-layer version. The distinction matters across the memory market because manufacturing high-performance HBM can consume more than three times the wafer capacity required for conventional DRAM. Continued AI demand could therefore keep supplies of standard memory tight even as producers add capacity.

SK hynix unveiled a 48-gigabyte, 16-layer HBM4 chip at the CES technology show in Las Vegas in January. The product offers one-third more capacity than the company’s 36GB, 12-layer version. SK hynix began supplying HBM4 to major customers in the second quarter and has expanded production, although it has not publicly confirmed a supply-chain report that it started volume shipments of 16-layer chips for Rubin.

At a Taiwan Semiconductor Manufacturing Co. technology conference in September, SK hynix displayed a Vera Rubin superchip fitted with its 12-layer, 36GB HBM4 while presenting the 16-layer product separately. The display highlighted the gap between making a higher-capacity chip available and securing its adoption in a commercial AI system.

Samsung has shipped commercial HBM4 products since February, with its 12-layer lineup providing capacity of up to 36GB. The company said during its fourth-quarter earnings call in January that demand for 16-layer HBM4 remained limited and that large-scale commercialization was not immediately required. Samsung nevertheless said its 16-layer stacking technology was ready for mass production if customer requirements changed.

Samsung is also developing hybrid copper bonding technology for memory stacks of 16 layers or more. The approach is intended to reduce thermal resistance, an increasingly important challenge as manufacturers place more DRAM dies in each package.

The competition will depend on more than layer counts. HBM must be integrated with graphics processors through advanced packaging, including TSMC’s chip-on-wafer-on-substrate process. Limited packaging capacity could restrict finished AI accelerator supply even if memory output is sufficient. SK hynix has been working with TSMC to optimize that integration.

For the Korean memory leaders, 16-layer HBM4 is therefore a preparation for future AI systems that require more capacity rather than an immediate volume driver. Production yields, heat management and compatibility with foundry packaging are likely to determine how quickly the technology moves from demonstration to widespread deployment.